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Espressif Systems /ESP32-S3 /ASSIST_DEBUG /CORE_1_INTR_ENA

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Interpret as CORE_1_INTR_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_1_AREA_DRAM0_0_RD_INTR_ENA)CORE_1_AREA_DRAM0_0_RD_INTR_ENA 0 (CORE_1_AREA_DRAM0_0_WR_INTR_ENA)CORE_1_AREA_DRAM0_0_WR_INTR_ENA 0 (CORE_1_AREA_DRAM0_1_RD_INTR_ENA)CORE_1_AREA_DRAM0_1_RD_INTR_ENA 0 (CORE_1_AREA_DRAM0_1_WR_INTR_ENA)CORE_1_AREA_DRAM0_1_WR_INTR_ENA 0 (CORE_1_AREA_PIF_0_RD_INTR_ENA)CORE_1_AREA_PIF_0_RD_INTR_ENA 0 (CORE_1_AREA_PIF_0_WR_INTR_ENA)CORE_1_AREA_PIF_0_WR_INTR_ENA 0 (CORE_1_AREA_PIF_1_RD_INTR_ENA)CORE_1_AREA_PIF_1_RD_INTR_ENA 0 (CORE_1_AREA_PIF_1_WR_INTR_ENA)CORE_1_AREA_PIF_1_WR_INTR_ENA 0 (CORE_1_SP_SPILL_MIN_INTR_ENA)CORE_1_SP_SPILL_MIN_INTR_ENA 0 (CORE_1_SP_SPILL_MAX_INTR_ENA)CORE_1_SP_SPILL_MAX_INTR_ENA 0 (CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA)CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA 0 (CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA)CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA

Description

Core1 monitor interrupt enable register

Fields

CORE_1_AREA_DRAM0_0_RD_INTR_ENA

Core1 dram0 area0 read monitor interrupt enable
CORE_1_AREA_DRAM0_0_WR_INTR_ENA

Core1 dram0 area0 write monitor interrupt enable
CORE_1_AREA_DRAM0_1_RD_INTR_ENA

Core1 dram0 area1 read monitor interrupt enable
CORE_1_AREA_DRAM0_1_WR_INTR_ENA

Core1 dram0 area1 write monitor interrupt enable
CORE_1_AREA_PIF_0_RD_INTR_ENA

Core1 PIF area0 read monitor interrupt enable
CORE_1_AREA_PIF_0_WR_INTR_ENA

Core1 PIF area0 write monitor interrupt enable
CORE_1_AREA_PIF_1_RD_INTR_ENA

Core1 PIF area1 read monitor interrupt enable
CORE_1_AREA_PIF_1_WR_INTR_ENA

Core1 PIF area1 write monitor interrupt enable
CORE_1_SP_SPILL_MIN_INTR_ENA

Core1 stackpoint overflow monitor interrupt enable
CORE_1_SP_SPILL_MAX_INTR_ENA

Core1 stackpoint underflow monitor interrupt enable
CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA

IBUS busy monitor interrupt enable
CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA

DBUS busy monitor interrupt enbale

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data